Some semiconductor memory devices adopt a hierarchical structure having a global bit line and a local bit line due to a reading speed and also to prevent an erroneous operation caused by cell leakage.
In such a semiconductor memory device, charging and discharging occurs in both the local bit line and the global bit line when reading data, leading to large power consumption.
Also, the reading speed of data depends on the cell current and there is a problem that the reading speed is slow. Further, there are circuits other than the cells (a precharge/discharge circuit, a column selector, S/A (sense amplifier), and a buffer) for each bank, which increases the area of the bank.